`include "defines.v"

module IF_Stage (
    input  wire clk,
    input  wire rst,
    input  wire load_use_stall,

    input  wire         pc_sel,        //pc source control
    input  wire [63: 0] pc_jorb,       //Branch/Jump addr
    
    input  wire [`INSTLEN] im_data_i,

    output wire [`INSTLEN] im_data_o,
    output wire            inst_ena,
    output reg  [63: 0] pc
);

assign im_data_o = im_data_i;
assign inst_ena  = ( rst == 1'b1 ) ? 0 : 1;

always@(posedge clk)
begin
    if(rst) begin 
        pc <=`PC_START;
    end
    else if (pc_sel)begin
        pc <= pc_jorb;
    end
    else if (load_use_stall) begin
        pc <= pc;
    end
    else begin
        pc <= pc + 4; 
    end
end

endmodule